HW/SW Co-Design for a Reactive Processor

This paper presents an approach to accelerate reactive processing via an external logic block that handles complex signal expressions. A reactive program, programmed in the synchronous language Esterel, is synthesized into a software component, running on the Kiel Esterel Processor, and a hardware component, consisting of simple combinational logic. The transformation process involves a two-step procedure, which first partitions the program at the source level and subsequently performs the synthesis. An intermediate logic minimization, at the source code level, facilitates the synthesis of compact logic blocks.